1. Field of the Invention
The invention relates to the construction of a vertical diffused metal oxide semiconductor (DMOS) transistor structure and more particularly relates to the avoidance of parasitic elements in such structures. DMOS transistors have been developed to supplement the well-known planar insulated gate field effect transistor (IGFET) structures. U.S. Amlinger Pat. No. 3,412,297 discloses a vertical DMOS transistor having a channel length of less than a micron. The teaching in this patent is incorporated herein by reference. The basic structure is a high frequency NPN transistor having a base about 0.5 micron thick. This NPN structure is etched to expose the edges of the various layers and a gate oxide is grown over the exposed edges. When a gate metal is formed over the gate oxide it confronts the edge of the thin base. Then when the structure is biased the gate metal potential will act to modulate the current flowing across the edge of the thin base P region. Since the P region is typically only about one-half micron thick the resulting DMOS will have a channel length of less than a micron. While not shown in the patent, the NPN transistor will act in parallel with the DMOS and thereby create a parasitic parallel-connected bipolar transistor that can be biased into conduction. Such conduction is localized and can result in localized heating which in turn results in greater conduction. This behavior can be a regenerative and destructive process.
2. Description of the Prior Art
The Amlinger patent shows a prior art version of a vertical DMOS transistor that employs a metal gate electrode. The invention makes use of a silicon gate which is created by trench etching and a conductive polycrystalline silicon (polysilicon) backfill. FIG. 1 shows a silicon gate vertical DMOS transistor which makes use of trench etching. While Amlinger shows a broad trench etched into a vertical NPN transistor, FIG. 1 show a narrow, sharply defined, trench etched within the confines of the NPN transistor emitter and made deep enough to fully penetrate the base region. Thus, the emitter surrounds the trench.
In FIG. 1, the semiconductor starting wafer is an N+ substrate 10 having grown thereon an epitaxial N type layer 11. Layer 11 has diffused therein a heavily doped P+ transistor base contact region 12 and a central P type base region 13. Base contact region 12 is normally made in the form of a peripheral ring that is shaped to provide the desired transistor topography. Emitter N+ diffused region 14 is located within base region 13 and extends only part way therethrough. A trench is etched through the resultant NPN transistor in the center of the emitter and the etching is extended so as to fully penetrate the base region 13. The trench walls are oxidized to create gate oxide 15 and it is filled with conductive polysilicon 16 which forms the DMOS transistor gate. Contact metal 17, which is applied over the silicon surface, shorts regions 14 and 12 together to provide the source electrode. It can be seen that region 13 forms the DMOS transistor channel region which can be rendered conductive where it abuts the gate oxide 15 by the potential applied to the gate 16. When the gate potential is made sufficiently positive with respect to metal layer 17 (the DMOS body contact) an adjacent N type channel can be created to pass electrons from source 14 to drain 11.
As will be seen in the subsequent discussion, the structure of FIG. 1 can be constructed using well-known processing steps. However, it has a serious drawback. The vertical DMOS transistor is connected in parallel with an NPN bipolar transistor. Since this parasitic NPN transistor has is emitter connected to its base by metal 17 it cannot normally be turned on. However, it can be seen that the inner confines of region 13 are some distance away from region 12 and this establishes a lateral resistance. If sufficient base current is caused to flow laterally, for example due to a drain transient, the NPN bipolar transistor can be momentarily turned on by the voltage drop that exists across the base resistance. Once such conduction starts it can locally heat the silicon and create a runaway condition that will grow and destroy the transistor. This phenomenon is well-known in bipolar power transistors which are typically ballasted to avoid the problem.